ADXL345 (Rev. G) - adxl345.pdf
www.analog.com/media/en/technical-documentation/data-sheets/adxl345.pdf
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If power is applied to the ADXL345 before the clock polarity and phase of the host processor are configured, the CS pin should be brought high before changing the clock polarity and phase.
This line must go low at the start of a transmission and high at the end of a transmission
SCLK should idle high during a period of no transmission
the mul- tiple-byte bit
R/W bit in the first byte transfer
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